BIST for Jitter Measurement and Jitter Decomposition of CDR

This paper describes a Built-In-Self-Test (BIST) circuit that tests the relative timing jitter of NRZ data and recovered clock of PLL-based CDR. Using the jitter information, the bit error rate and peak to peak jitter can be estimated. This BIST circuit doesn’t need a high resolution and high accuracy delay line to achieve high accuracy measurement. It depends on calibration and curve fitting algorithm to have high accuracy timing and estimate total jitter magnitude. Calibration can be simply done by switching the VCO into free running mode and the accuracy can be as high as possible at the expense of time. This BIST circuit also extracts DJ and RJ by adopting the bathtub curve fitting algorithm to estimate total jitter at BER=10 level.